Faculty of Engineering Ain shams University
Electrical Engineering, Electronics and Electrical Communications - very Good
2017 - 2022
graduation project degree: Excellent
Education
Graduation Project
High Speed Serial Link Transceiver for DDR5 PHY IP
Sponsored By Si-Vision. Supervised By Dr. Theodora
Responsible for Designing The LoopBack receiver which is used to test the Transceiver performance i.e. Bit Error Rate and 8-Bit DAC used to generate DC Voltage reference internally on die.
Tasks:
- Writing Behavioral Verilog-A Model for the DAC and LoopBack Rx .
- Designing the DAC and LoopBack Rx.
- Layouting the LoopBack Rx (Amp -Comparator -S-R latch).
Internships and trainings
Si Vision academy - Layout track -July 2022 To present
sponsored by Synopsys
Siemens EDA (mentor graphics)- February 2021 To February 2021
Data converters Design and Verification, supervised by Dr. Hesham Omran
certificate:https://cutt.us/iE7yM
Analog IC Design Workshop -July 2021 To Sep 2021
Practiced Designing and simulating various analog blocks on Cadence Virtuoso.
Information Technology Institue(ITI) -August 2020 To Septemper 2020
Analog IC Design supervised by Dr. Hesham Omran
certificate: https://shorturl.at/cmoKY
Projects
Strong Arm comparator Layout TSMC65nm
Diff-Amplifier Layout TSMC65nm
Digital gates Layout (standard cell)
10Gbps Front End Serial Link Receiver (Amp + CTLE + Buffer)
7 bit segmented current steering DAC using TSMC65nm
5 bit current steering DAC
Bandgap Reference Circuit using TSMC65nm
Folded Cascode -OTA using Tsmc65nm
Two stage miller OTA using Tsmc65nm
Fully differential Folded Cascode with CMFB network using umc120nm
Telescopic-OTA using Tsmc65nm
5T-OTA using Tsmc65nm
Full Custom 4 bit ALU
Embedded system: smart car parking system
Skills
IC Layout Design
Matching Techniques
Isolation
Shielding
DRC
LVS
PEX
Analog IC Design
Analog Circuits
Gm/Id Methodology
Tools
Cadence IC Custom Design tools
Calibre DRC/LVS/PEX