Summary

Currently a full-time AMS design engineer at Mediatek & Masters student at Ain Shams university who is eager to learn state of the art technology in Analog/mixed signal IC design, analyze complex problems and design the technology of the future

Birthdate

June 29, 1999

Gender

Male

Nationality

Egyptian

Residence

36 Nozha St. Ard el Golf - Cairo, Egypt

Work Experience

Mediatek

Senior AMS design engineer

January 2025 - Now

Currently responsible for the design of a high speed VCO at 12GHz for 224Gbps PAM4/6/8 Solutions

Infinilink

AMS design engineer

August 2022 - January 2025

participated in the Design of ultra high speed SerDes solutions up to 224G data rates in deep sub-micron technologies (5nm,4nm,3nm,…) with experience in the following areas

  • Design of high speed serializers, high speed clock distribution & calibration
  • Design of high speed pre-drivers & drivers (up to 16Gbps) supporting different termination schemes
  • Design of high precision bandgap circuits employing chopping and dynamic element matching
  • Design of V2V and V2I circuits for generation of different types of current and voltage references
  • EM/IR debugging and verification flows
  • Aging & reliability verification flows
  • Implementation/simulation & verification of behavioral models and performing AMS co-simulations

Education

Faculty of Engineering, Ain Shams university

Electronics & communications engineering - Masters of Science (MSc)

2023 - 2027

Cumulative GPA: 4.0

Faculty of Engineering, Ain Shams University

Electronics & Communications

2017 - 2022

Grade: Distinction with honors (Ranked 3rd on class)

Nefertari International School

Math Section

2003 - 2017

Grade: 97%

Projects

A 3.2 GS/s FIR DAC for a massive MIMO 5G transceiver

Granduation Project

Design flow:

1-Literature survey of RF vs FIR DACs for suitable implementation in the 28 Ghz sub band

2-System design of the chosen FIR DAC on matlab and simulink.

3-circuit level design of the FIR DAC and verification with system level matlab model.

A 7-bit segmented current steering DAC

Courses and Certificates

Languages

Language

Arabic

Mother Tongue

Language

English

Fluent