Graduation Year
2023
Birthdate
30/12/2000
Military status
Exempted
Graduation Year
2023
Birthdate
30/12/2000
Military status
Exempted
2018 - 2023
CGPA : 3.45 ( Ranked 11 th in 3rd year, 12 th in the overall result )
High Speed Serial Link Transceiver for USB 3.2. Supervised By Dr. EL Sayed Eid :(grade A+)
Responsible for designing PLL "Phase Locked Loop"system in transmitter and CDR "Clock and Data Recovery" System in Receiver.
Responsible for Transistor Level Design of Quadrature Phase VCO "Voltage Controlled Oscillator".
Participated in Charge Pump and Phase Detector Transistor Level Designs .
1. Analog IC Design1,2 : Supervised by Dr. Hesham Omran , ITI ("Information Technology Institute (ITI)") (got 94% in this course)
2. Analog Systems (ADCS and DACS) :Supervised by Dr. Hesham Omran ,Semeins EDA
3. Analog Mixed Signal Simulation and Modelling (AMS):Supervised by Dr. Hesham Omran ,Semeins EDA
4. AMS and Layout : Supervised by Dr. Hesham Omran and Dr. Sameh Ibrahim , ITI ("Information Technology Institute (ITI)").
5.RF Circuit Design (Taken in College )
Analog Design Skills
Expert in Electronic and Circuit Design ,Verilog-A ,Cadence IC Custom Design tools .
Excellent understanding of RF design and Digital IC Design basics .
Programming Skills
MATLAB ,C programming
others
Expert in simulation programs : (Cadence (Spectre), Ltspice , Multisim, ADT )
Expert in Math and Signal Processing
Experienced Fast Learner.
Skillful at teamwork .
Excellent Presentation Skills .
Skilled at Explaining complex topics and simplifying them .
Has a good experience in hardware lab equipment (Oscilloscopes and Signal Generators,already has my own lab equipment and kits)
Miller OTA ,Folded Cascode OTA
Differential Charge Pump,Frequency divider using Tspc D flip flop
Mixer circuit using Differential amplifier,Analog Multiplier Circuit using Gilbert cell,
CTLE (Continuous Time Linear Equalizer),VGA (Variable Gain Amplifier)
SAR ADC (Verilog A)
July 2023 - Now