Faculty of Engineering, Alexandria University September 2018 - July 2023
Department: Electronics and Communication Engineering
Grade: Excellent, 3.29 'GPA'
Education
Graduation Project
High Speed Serial Link Transceiver for USB3.1 Standard, Supervised by Dr. Sayed Eid.
The main focus of the project is to model, design, layout and verify the USB3.1 (GEN2) PHY transceiver.
was Responsible for RX Equalization. Verilog-A Modeling, Designing, Verifying and Layouting of all the following blocks:
● CTLE (Common Source with Degeneration Topology).
● 1-Tap DFE (Multiplexed Half Rate Architecture) with all its supporting circuits e.g.(Dynamic Comparator, SR Latch, GM Cell, CML MUX).
Internships and Trainings
AMS SerDes Design and Layout, Information Technology Institute (ITI) July 2023 - October 2023
-Understanding and Practicing many SerDes blocks e.g.(Tx Drivers, Pre-Drivers, Tx FFE, RX VGA, CTLE, Comparators, and DFE), Supervised by Prof. Sameh Ibrahim.
-Understanding and Practicing many Layout topics e.g.(CMOS Fabrication, Layout Effects, Custom Digital Cells, Analog Layout Techniques, Noise and Isolation, Floorplanning), Supervised by Eng. Islam Naashat. (Certificated)
AMS Simulation and Modeling Training, Mentor (Siemens EDA) July 2022 - September 2022
Understanding and Practicing SPICE Simulation, AMS Behavioral Modeling Using VerilogA, Supervised by Prof. Hesham Omran. (Certificated)
Analog IC Design Workshop September 2021 - December 2021
Design Many Analog Blocks Using Cadence Tool, Supervised by Eng. Ahmed Abdelati. (Self-Study)
Information Technology Institute (ITI) August 2021 - September 2021
Analog IC Design, Supervised by Prof. Hesham Omran. (Certificated)
Skills
Analog Circuit Design
Analog Circuits
High Speed Serial Links Circuits
Verilog-A
VLSI Fabrication Technology
IC layout
Cadence IC Custom Design tools
Digital Circuit Design
Static and Dynamic Combinational Logic Circuits
Sequential Logic Circuits