Mohanad Kamel

Analog Layout Engineer SerDes Team.

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Sample of Analog IPs Worked on: Sar ADCs, DACs, SerDes (C10/C20 and Central IP).

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Experience:

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1)Implementation of analog layouts consisting of the following tasks:

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a) Layout floorplan at blocks level (comparators, voltage reference blocks)

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b) Design layout taking into consideration:

i) Design constraints (C/R parasitic)

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ii) Layout effects (ex: WPE,STI)

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iii) Electromigration and voltage drop (EMIR)

c)Running physical checks on block and top IP levels (DRC/LVS/ERC)

d) Writing detailed documentation that summarizes the layout design.

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2. Fluent in the both planner and FinFet technologies (nodes from 40nm-4nm)

The majority of the tasks last year were in SS4 and GF12.

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3 Fluency in Custom Compiler

4. Knowledge of Unix commands.

5. Direct communication (written and oral) with circuit designers.

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Main contributions were for the following circuits:

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1. Switch capacitive DACS: Hgh Speed (GSPS) and Low Speed (2.5MH2).

2.voltage reference blocks (SS4 bandgap Central-IP/ vreg blocks in RX and TX)

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3. Serializer sub-blocks in TX.

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4. Calibration blocks in TX and RX.

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5.Blocks that contain differential pairs and current mirrors.

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6.Custom logic blocks

Customer support engineer specialized in server virtualization

Current Position: Analog Layout Engineer SerDes Team.