Over 13 years of dedicated experience in digital design. Responsible for the WiFi chip and MCU SOC design and IP design . Proficient in ASIC flow ,SOC , MCU Architecture , Low power technology ,Trust Zoon and Security technology ,WIFI MAC and so on . Solid Verilog design and implementation skills. Versed in collaborating with international teams. Provide technical leadership and guidance to junior engineers in design area.
Summary
Work Experience
NXP恩智浦
Wireless Connectivity Security ,SOC team, Digital Design Engineer
December 2019 - February 2025
Marvell美满电子
Design Verification Engineer
September 2011 - December 2019
Education
西安交大 XIANJIAOTONG University
集成电路设计 IC Design - Master
2008 - 2011
西安交大 XIANJIAOTONG University
自动化Automation Science and Technology - Bachelor
2004 - 2008
Skills
Familiar with MCU Architecture and IPs .
Familiar with TrustZone technology and Security IPs
Familiar with Low power methodology.
Familiar with ASIC Flow and EDA tool. Verilog and UVM .
Familiar with NPU IP and Machine Learning
Familiar with WIFI 802.11 protocol .AMBA protocol (AXI AHB APB) ..
Excellent communication skill in written and spoken English
Projects
4x4 Tri-Band CTW Wi-Fi 7 eMLSR + Dual-NB chip
February 2023 - February 2025
Responsible for some design tasks in MAC for WIFI chips , Especially AXI DMA IP design .
Architecture design and function definition for AXI DMA IP which achieved MAC's TX/RX and multiple modules accessing memory and host .
Release design specifications, RTL coding, and provided verification support. Developed advanced outstanding and out-of-order functions to enhance performance.
In WIFI projects, familiar MAC and lead SH team to collaborate across region to ensure high quality and on time releases.
Cross-Over MCU Processor with Machine Learning (ML) capabilities
January 2024 - October 2024
Designed the high-performance subsystem COMPUTE_SS of the MCU, which handling both control and data processing tasks.
Focused on subsystem architecture, documents specification, top and hierarchy definition, IP integration( including ARM CortexM55, Neural Processing Unit (NPU), Security IP, and Fabric...), Lint clean , Synthesis and PPA Analysis. Demonstrating professional design skills.
Maintained smooth communication with related teams . Conducted task analysis and partitioning, tracked project schedules and quality, and emphasized the release process. Successfully released the subsystem following a standardized flow.
A highly integrated, low-power Wireless MCU with an integrated MCU and Wi-Fi 6 + Bluetooth
January 2020 - January 2023
Successfully completed the chip tape-out. Responsible for MCU related design tasks:
- Defined MCU architecture, bus matrix, memory map, and TrustZone, and handled SOC related tasks.
- Designed the PMU (power management unit).
- Led and integrated IPs including CPU Arm® Cortex® - M33, Flash Controller, Ethernet, USIM, LCDIC, analog IPs, and security IPs...
- Provided support for synthesis, STA, lint, CDC and PPA analysis .
- Supported DV, silicon bring - up, and validation
Low-power Microcontroller System-on-Chip (SoC)
January 2016 - December 2019
Participated in the design of low-power Microcontroller SoC . Among three chip families, two were successfully mass produced and one was successfully taped out.
Responsible for the architecture design of the MCU, bus matrix, memory map, and TrustZone. I also took charge of designing, optimizing, integrating, maintaining, and releasing IPs, including SSP, I2S, SPI, LCDIC, Flash Controller, USIM, etc.
Moreover, I handled tasks like Lint, CDC, IO timing analysis, and Conformal ECO.
WIFI chips (11ax 8x8 WIFI and 11ax 4x4 WIFI )
August 2016 - August 2019
Participated in the MAC design of two WIFI chips (11ax 8x8 Wi - Fi and 11ax 4x4 Wi - Fi), both of which were successfully put into production.
Responsible for the design, optimization, and maintenance of IPs such as Beamforming (directing transmitter signals towards the receiver in a specific direction) and AXI DMA.
New IP , Flash Controller's design
January 2016 - December 2016
Design of a new IP, the Flash Controller. Successfully released it for use in two projects and into production.
The Flash Controller establishes a communication link between the processor and on chip or off chip Flash memory. It features an XIP (execute in place) function to reduce internal SRAM size and an On The Fly decryption engine for secure access.
Took charge of all design aspects, including defining and writing design specifications to meet requirements, architecture design, RTL coding, synthesis ,analyzing and optimizing critical timing paths, and lint /CDC .