NXP恩智浦
Wireless SOC Team , Design Engineer
December 2019 - Now
Marvell美满电子
Design Verification Engineer
September 2011 - December 2019
Work Experience
Education
西安交大 XIANJIAOTONG University
自动化Automation Science and Technology - Bachelor
2004 - 2008
西安交大 XIANJIAOTONG University
集成电路设计 IC Design - Master
2008 - 2011
Skills
Familiar with Verilog and UVM .Familiar with AMBA protocol , AXI AHB APB ...
Familiar with MCU architecture and IPs .
Familiar with TrustZone technology and Security IPs
Familiar with Low power methodology.
Familiar with ASIC Flow and EDA tool
Excellent communication skill in written and spoken English
Projects
The project that a highly integrated, low-power Wireless MCU with an integrated MCU and Wi-Fi 6 + Bluetooth
January 2020 - Now
Chip already taped out successfully .Be responsible for MCU related design tasks : 1.MCU architecture/bus matrix /memory map/TrustZone definition and SOC related tasks 2. PMU (power management unit) design 3. Lead and Integrate IPs , such as CPU Arm® Cortex®-M33, Flash Controller , Ethernet , USIM , LCDIC... Analog IPs And Security IPs 4. Support synthesis/STA/lint/CDC... 5. Support DV / Silicon bring up and validation .
Low-power Microcontroller System-on-Chip (SoC)
January 2016 - December 2019
Participating in design of the low-power Microcontroller System-on-Chip (SoC) . Three family chips ， Two are production successfully and one are taped out successfully . Be responsible for MCU/bus matrix /memory map/TrustZone architecture, , Be responsible for designing /optimizing /integration /maintaining/ releasing of IPs , such as SSP /I2S/ SPI/ LCDIC/ Flash Controller / USIM/ ... Be responsible for Lint /CDC/ IO Timing analysis/Conformal ECO and so on .
WIFI chips (11ax 8x8 WIFI and 11ax 4x4 WIFI )
August 2016 - August 2019
Participating in MAC design of two WIFI chips (11ax 8x8 WIFI and 11ax 4x4 WIFI ) . Both are production successfully . Be responsible for designing /optimizing /maintaining IPs : Beamforming (which is about focusing transmitter signal in a specific direction towards the receiver) ; AXI DMA and so on .
New IP , Flash Controller's design
January 2016 - December 2016
Responsible for the New IP , Flash Controller's design . Released IP to two project and production successfully .
Flash Controller provides a communication path between the Processer and the on-chip or off-chip Flash memory , Contains XIP (execute in place ) function to decrease the internal SRAM size , and On-The-Fly decryption engine for securely accessing.
Be Responsible for all design tasks ,Definition and writing of design specification to meet all requirements . Architecture ,implementing and RTL coding . Critical timing path analysis and optimize . Synthesis and so on .