Birthdate
1-6-1999
Nationality
Egyptian
Military status
1st Half
Personal Information
Education
Bachelor’s degree
2017 - 2022
- Faculty of Engineering, Fayoum University.
- Electronics, and communications engineering.
- Cumulative grade: very good with honor
Graduation Project
High Speed Serial Link Data Transceiver. September 2021 - Present
- Design a USB3.1 Transceiver to reach 10Gbps.
- System modeling using** Verilog-A **and MATLAB to extract each block specs and use it as a guide for implementation.
- Literature survey to choose the best topologies for CTLE, VGA, and Charge Pump.
- Implementation of CTLE and VGA in 65nm technology node in **Cadence Virtuoso **with output data rate **10Gbps **and minimum power and area.
- Implementation of Charge Pump of CDR in 65nm technology node in Cadence Virtuoso.
Experience
Internships:
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March 5554 - February 5454
- Participated in Si–Vision Contest 2020. (Achieved the** Second **place) (Sep – Oct 2020)
- High Precision BGR including corners and mismatch verifications.
- Analog IC Design Trainee at Information Technology Institute (ITI) supervised by **Dr. Hesham Omran. **(Aug – Sep 2021)
- Develop test benches and use sizing chart and GM/ID curves.
- Overview on the different Differential amplifier and** Current mirror** topologies.
- Analog/Mixed-Signal Simulation and Modeling ( **Siemens EDA **) (Aug – Sep 2021)
- Creating a simple circuit simulator from scratch and studying BSIM models.
- Modeling and simulation of complex mixed-signal systems using** Verilog-A.**
- Analog Integrated System Design ( Siemens EDA ) (Feb – Mar 2022)
- Data converters specifications and testing.
Projects
High Precision Band Gap Reference design using TSMC 65nm.
- Circuit design to achieve certain figure of merit with corners and **Monte Carlo **simulations.
fully differential SAR ADC design and verification.
- **Verilog-A **behavioral models for basic digital building blocks.
- Circuit design of Capacitive DAC & bottom-plate switch.
Analog IC design – Fully differential folded cascade OTA
- Design and simulation of folded cascode OTA with capacitive feedback, behavioral and actual CMFB network.
Analog IC design – Two-stage Miller OTA.
- Design procedure and simulation of two-stage Miller OTA, frequency compensation, RHP zero, verification.
PLL Design and Verilog-A Behavioral Modeling
- Top-down design methodology, e.g., using Cadence Virtuoso “Hierarchy Editor” tool.
Design and Layout of NAND gate circuit.
32Bit CPU processor single cycle and pipeline project.
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Courses and Certificates
• CMOS Analog IC design at Information Technology Institute (ITI).
Analog/Mixed-Signal Simulation and Modeling (Siemens EDA).
Analog Integrated System Design (Siemens EDA).
Programing for Everybody (Python) course.
Skills
Technical Skills
• Analog/RF design •Communication systems •VLSI technology •Custom digital design •Python •C++
Tools
• Cadence Virtuoso • MATLAB • Visual studio • Proteus • Multisim • Quartus • Logisim • Microsoft office
Skills Highlights
• self-motivated • hard-working • Problem Solving Skills • Presentation Skills • Communication Skills • Quick learner